Built-in Steps and their Configuration Variables¶
These steps are included with OpenLane and are used by its various built-in flows.
This page documents these steps, how to get them and their configuration variables (if applicable).
If you’re looking for documentation for the Step
Python classes themselves,
check the API reference here.
Warnings
Two steps in a given Flow may share a configuration variable name if-and-only-if the variables are otherwise identical, i.e., the name, type, and default value all match. Otherwise, the flow will not compile.
Some steps have a variable prefixed with
RUN_
that enables or disables said step. This is a vestige from OpenLane 1 and it is recommended to explicitly specify your flow either by using the API or in your JSON configuration file’smeta
object.
Notes
?
indicates an optional variable, i.e., a value that may hold a value ofNone
. OpenLane steps are expected to understand that these values are optional and behave accordingly.Variable names denoted (PDK) are expected to be declared by the PDK.
If a PDK does not define one of the required variables, it is considered to be incompatible with this step.
Tip
For a table of contents, press the following button on the top-right corner
of the page:
Checker¶
Disconnected Pins Checker¶
Raises an immediate error if critical disconnected pins (metric: design__critical_disconnected_pin__count
) are >= 0. Doesn’t raise an error depending on error_on_var if defined.
Importing
from openlane.steps.checker import DisconnectedPins
# or
from openlane.steps import Step
DisconnectedPins = Step.factory.get("Checker.DisconnectedPins")
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Checks for disconnected instance pins after detailed routing and quits immediately if so. |
|
Hold Timing Violations Checker¶
Raises a deferred error if NotImplemented (metric: timing__hold_vio__count
) are >= 0. Doesn’t raise an error depending on error_on_var if defined.
Importing
from openlane.steps.checker import HoldViolations
# or
from openlane.steps import Step
HoldViolations = Step.factory.get("Checker.HoldViolations")
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
List[str] |
A list of wildcards matching IPVT corners to use during checking for timing violations. |
|
|
|
List[str]? |
A list of wildcards matching IPVT corners to use during checking for hold violations. |
|
Spice Extraction-based Illegal Overlap Checker¶
Raises a deferred error if Magic Illegal Overlap errors (metric: magic__illegal_overlap__count
) are >= 0. Doesn’t raise an error depending on error_on_var if defined.
Importing
from openlane.steps.checker import IllegalOverlap
# or
from openlane.steps import Step
IllegalOverlap = Step.factory.get("Checker.IllegalOverlap")
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Checks for illegal overlaps during Magic extraction. In some cases, these imply existing undetected shorts in the design. It raises an error at the end of the flow if so. |
|
KLayout Design Rule Checker¶
Raises a deferred error if KLayout DRC errors (metric: klayout__drc_error__count
) are >= 0. Doesn’t raise an error depending on error_on_var if defined.
Importing
from openlane.steps.checker import KLayoutDRC
# or
from openlane.steps import Step
KLayoutDRC = Step.factory.get("Checker.KLayoutDRC")
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Checks for DRC violations after KLayout DRC is executed and exits the flow if any was found. |
|
Layout vs. Schematic Error Checker¶
Raises a deferred error if LVS errors (metric: design__lvs_error__count
) are >= 0. Doesn’t raise an error depending on error_on_var if defined.
Importing
from openlane.steps.checker import LVS
# or
from openlane.steps import Step
LVS = Step.factory.get("Checker.LVS")
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Checks for LVS errors after Netgen is executed. If any exist, it raises an error at the end of the flow. |
|
Lint Errors Checker¶
Raises an immediate error if Lint errors (metric: design__lint_error__count
) are >= 0. Doesn’t raise an error depending on error_on_var if defined.
Importing
from openlane.steps.checker import LintErrors
# or
from openlane.steps import Step
LintErrors = Step.factory.get("Checker.LintErrors")
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Quit immediately on any linter errors. |
|
Lint Timing Errors Checker¶
Raises an immediate error if Lint Timing Errors (metric: design__lint_timing_construct__count
) are >= 0. Doesn’t raise an error depending on error_on_var if defined.
Importing
from openlane.steps.checker import LintTimingConstructs
# or
from openlane.steps import Step
LintTimingConstructs = Step.factory.get("Checker.LintTimingConstructs")
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Quit immediately on any discovered timing constructs during linting. |
|
Lint Warnings Checker¶
Raises an immediate error if Lint warnings (metric: design__lint_warning__count
) are >= 0. Doesn’t raise an error depending on error_on_var if defined.
Importing
from openlane.steps.checker import LintWarnings
# or
from openlane.steps import Step
LintWarnings = Step.factory.get("Checker.LintWarnings")
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Raise an error immediately on any linter warnings. |
|
Magic Design Rule Checker¶
Raises a deferred error if Magic DRC errors (metric: magic__drc_error__count
) are >= 0. Doesn’t raise an error depending on error_on_var if defined.
Importing
from openlane.steps.checker import MagicDRC
# or
from openlane.steps import Step
MagicDRC = Step.factory.get("Checker.MagicDRC")
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Checks for DRC violations after magic DRC is executed and exits the flow if any was found. |
|
Maximum Capacitance Violations Checker¶
Raises a deferred error if NotImplemented (metric: design__max_cap_violation__count
) are >= 0. Doesn’t raise an error depending on error_on_var if defined.
Importing
from openlane.steps.checker import MaxCapViolations
# or
from openlane.steps import Step
MaxCapViolations = Step.factory.get("Checker.MaxCapViolations")
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
List[str] |
A list of wildcards matching IPVT corners to use during checking for timing violations. |
|
|
|
List[str]? |
A list of wildcards matching IPVT corners to use during checking for max cap violations. |
|
Maximum Slew Violations Checker¶
Raises a deferred error if NotImplemented (metric: design__max_slew_violation__count
) are >= 0. Doesn’t raise an error depending on error_on_var if defined.
Importing
from openlane.steps.checker import MaxSlewViolations
# or
from openlane.steps import Step
MaxSlewViolations = Step.factory.get("Checker.MaxSlewViolations")
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
List[str] |
A list of wildcards matching IPVT corners to use during checking for timing violations. |
|
|
|
List[str]? |
A list of wildcards matching IPVT corners to use during checking for max slew violations. |
|
Netlist Assign Statement Checker¶
Raises a StepError if the Netlist has an assign
statement in it.
assign
statements are known to cause bugs in some PnR tools.
Importing
from openlane.steps.checker import NetlistAssignStatements
# or
from openlane.steps import Step
NetlistAssignStatements = Step.factory.get("Checker.NetlistAssignStatements")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
Verilog Netlist (.nl.v) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Whether to emit an error or simply warn about the existence |
|
Power Grid Violation Checker¶
Raises a deferred error if power grid violations (as reported by OpenROAD PSM- you may ignore these if LVS passes) (metric: design__power_grid_violation__count
) are >= 0. Doesn’t raise an error depending on error_on_var if defined.
Importing
from openlane.steps.checker import PowerGridViolations
# or
from openlane.steps import Step
PowerGridViolations = Step.factory.get("Checker.PowerGridViolations")
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Checks for unconnected nodes in the power grid. If any exists, an error is raised at the end of the flow. |
|
Setup Timing Violations Checker¶
Raises a deferred error if NotImplemented (metric: timing__setup_vio__count
) are >= 0. Doesn’t raise an error depending on error_on_var if defined.
Importing
from openlane.steps.checker import SetupViolations
# or
from openlane.steps import Step
SetupViolations = Step.factory.get("Checker.SetupViolations")
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
List[str] |
A list of wildcards matching IPVT corners to use during checking for timing violations. |
|
|
|
List[str]? |
A list of wildcards matching IPVT corners to use during checking for setup violations. |
|
Routing Design Rule Checker¶
Raises a deferred error if Routing DRC errors (metric: route__drc_errors
) are >= 0. Doesn’t raise an error depending on error_on_var if defined.
Importing
from openlane.steps.checker import TrDRC
# or
from openlane.steps import Step
TrDRC = Step.factory.get("Checker.TrDRC")
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Checks for DRC violations after routing and exits the flow if any was found. |
|
Wire Length Threshold Checker¶
Raises a deferred error if Threshold-surpassing long wires (metric: route__wirelength__max
) are >= the threshold specified in the configuration file.. Doesn’t raise an error depending on error_on_var if defined.
Importing
from openlane.steps.checker import WireLength
# or
from openlane.steps import Step
WireLength = Step.factory.get("Checker.WireLength")
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Checks if any wire length exceeds the threshold set in the PDK. If so, an error is raised at the end of the flow. |
|
Magic vs. KLayout XOR Difference Checker¶
Raises a deferred error if XOR differences (metric: design__xor_difference__count
) are >= 0. Doesn’t raise an error depending on error_on_var if defined.
Importing
from openlane.steps.checker import XOR
# or
from openlane.steps import Step
XOR = Step.factory.get("Checker.XOR")
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Checks for geometric differences between the Magic and KLayout stream-outs. If any exist, raise an error at the end of the flow. |
|
Yosys Synth Checks¶
Raises an immediate error if Yosys check errors (metric: synthesis__check_error__count
) are >= 0. Doesn’t raise an error depending on error_on_var if defined.
Importing
from openlane.steps.checker import YosysSynthChecks
# or
from openlane.steps import Step
YosysSynthChecks = Step.factory.get("Checker.YosysSynthChecks")
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Quits the flow immediately if one or more synthesis check errors are flagged. This checks for combinational loops and/or wires with no drivers. |
|
Unmapped Cells Checker¶
Raises an immediate error if Unmapped Yosys instances (metric: design__instance_unmapped__count
) are >= 0. Doesn’t raise an error depending on error_on_var if defined.
Importing
from openlane.steps.checker import YosysUnmappedCells
# or
from openlane.steps import Step
YosysUnmappedCells = Step.factory.get("Checker.YosysUnmappedCells")
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Checks for unmapped cells after synthesis and quits immediately if so. |
|
KLayout¶
Design Rule Check (KLayout)¶
Importing
from openlane.steps.klayout import DRC
# or
from openlane.steps import Step
DRC = Step.factory.get("KLayout.DRC")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
GDSII Stream (.gds) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
Path |
A path to the KLayout layer technology (.lyt) file. |
|
|
|
Path |
A path to the KLayout layer properties (.lyp) file. |
|
|
|
Path |
A path to the KLayout LEF/DEF layer mapping (.map) file. |
|
|
|
Path? |
A path to KLayout DRC runset. |
|
|
|
Dict[str, (bool| |
Options passed directly to the KLayout DRC runset. They vary from one PDK to another. |
|
|
|
int? |
Specifies the number of threads to be used in KLayout DRCIf unset, this will be equal to your machine’s thread count. |
|
Open In GUI¶
Opens the DEF view in the KLayout GUI, with layers loaded and mapped
properly. Useful to inspect .klayout.xml
database files and the like.
Importing
from openlane.steps.klayout import OpenGUI
# or
from openlane.steps import Step
OpenGUI = Step.factory.get("KLayout.OpenGUI")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
Design Exchange Format (.def) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
Path |
A path to the KLayout layer technology (.lyt) file. |
|
|
|
Path |
A path to the KLayout layer properties (.lyp) file. |
|
|
|
Path |
A path to the KLayout LEF/DEF layer mapping (.map) file. |
|
|
|
bool |
Whether to run the KLayout GUI in editor mode or in viewer mode. |
|
|
|
bool |
Whether to prioritize GDS (if found) when running this step. |
|
Render Image (w/ KLayout)¶
Renders a PNG of the layout using KLayout.
DEF is required as an input, but if a GDS-II view exists in the input state, it will be used instead.
Importing
from openlane.steps.klayout import Render
# or
from openlane.steps import Step
Render = Step.factory.get("KLayout.Render")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
Design Exchange Format (.def) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
Path |
A path to the KLayout layer technology (.lyt) file. |
|
|
|
Path |
A path to the KLayout layer properties (.lyp) file. |
|
|
|
Path |
A path to the KLayout LEF/DEF layer mapping (.map) file. |
|
GDSII Stream Out (KLayout)¶
Converts DEF views into GDSII streams using KLayout.
The PDK must support KLayout for this step to work, otherwise it will be skipped.
If PRIMARY_GDSII_STREAMOUT_TOOL
is set to "klayout"
, both GDS and KLAYOUT_GDS
will be updated, and if set to another tool, only KLAYOUT_GDS
will be
updated.
Importing
from openlane.steps.klayout import StreamOut
# or
from openlane.steps import Step
StreamOut = Step.factory.get("KLayout.StreamOut")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
Design Exchange Format (.def) |
GDSII Stream (.gds) |
GDSII Stream (KLayout) (.klayout.gds) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
Path |
A path to the KLayout layer technology (.lyt) file. |
|
|
|
Path |
A path to the KLayout layer properties (.lyp) file. |
|
|
|
Path |
A path to the KLayout LEF/DEF layer mapping (.map) file. |
|
KLayout vs. Magic XOR¶
Performs an XOR operation on the Magic and KLayout GDS views. The idea is: if there’s any difference between the GDSII streams between the two tools, one of them have it wrong and that may lead to ambiguity.
Importing
from openlane.steps.klayout import XOR
# or
from openlane.steps import Step
XOR = Step.factory.get("KLayout.XOR")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
GDSII Stream (Magic) (.magic.gds) |
|
GDSII Stream (KLayout) (.klayout.gds) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
Path |
A path to the KLayout layer technology (.lyt) file. |
|
|
|
Path |
A path to the KLayout layer properties (.lyp) file. |
|
|
|
Path |
A path to the KLayout LEF/DEF layer mapping (.map) file. |
|
|
|
int? |
Specifies number of threads used in the KLayout XOR check. If unset, this will be equal to your machine’s thread count. |
|
|
|
List[str]? |
KLayout layers to ignore during XOR operations. |
|
|
|
int? |
A tile size for the XOR process in µm. |
|
Magic¶
Design Rule Checks¶
Performs design rule checking on the GDSII stream using Magic.
This also converts the results to a KLayout database, which can be loaded.
The metrics will be updated with magic__drc_error__count
. You can use
the relevant checker to quit if that number is
nonzero.
Importing
from openlane.steps.magic import DRC
# or
from openlane.steps import Step
DRC = Step.factory.get("Magic.DRC")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
Design Exchange Format (.def) |
|
GDSII Stream (.gds) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
A flag to choose whether labels are read with DEF files or not. From magic docs: “The ‘-labels’ option to the ‘def read’ command causes each net in the NETS and SPECIALNETS sections of the DEF file to be annotated with a label having the net name as the label text.” If LVS fails, try disabling this option. |
|
|
|
bool |
A flag to enable polygon subcells in magic for gds read potentially speeding up magic. From magic docs: “Put non-Manhattan polygons. This prevents interations with other polygons on the same plane and so reduces tile splitting.” |
|
|
|
bool |
If set to true, blockages in DEF files are ignored. Otherwise, they are read as sheets of metal by Magic. |
|
|
|
bool |
A flag to choose whether to include GDS pointers in the generated mag files or not. |
|
|
|
Path |
A path to the |
|
|
|
Path |
A path to a Magic tech file which, mainly, has DRC rules. |
|
|
|
Path |
A path to a PDK-specific setup file sourced by |
|
|
|
List[Path]? |
A list of pre-processed concrete views for cells. Read as a fallback for undefined cells. |
|
|
|
List[Path]? |
A list of pre-processed abstract LEF views for cells. Read as a fallback for undefined cells in scripts where cells are black-boxed. |
|
|
|
bool |
Capture errors print by Magic and quit when a fatal error is encountered. Fatal errors are determined heuristically. It is not guaranteed that they are fatal errors. Hence this is function is gated by a variable. This function is needed because Magic does not throw errors. |
|
|
|
bool |
A flag to choose whether to run the Magic DRC checks on GDS or not. If not, then the checks will be done on the DEF view of the design, which is a bit faster, but may be less accurate as some DEF/LEF elements are abstract. |
|
Open In GUI¶
Opens the DEF view in the Magic GUI.
Importing
from openlane.steps.magic import OpenGUI
# or
from openlane.steps import Step
OpenGUI = Step.factory.get("Magic.OpenGUI")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
Design Exchange Format (.def) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
A flag to choose whether labels are read with DEF files or not. From magic docs: “The ‘-labels’ option to the ‘def read’ command causes each net in the NETS and SPECIALNETS sections of the DEF file to be annotated with a label having the net name as the label text.” If LVS fails, try disabling this option. |
|
|
|
bool |
A flag to enable polygon subcells in magic for gds read potentially speeding up magic. From magic docs: “Put non-Manhattan polygons. This prevents interations with other polygons on the same plane and so reduces tile splitting.” |
|
|
|
bool |
If set to true, blockages in DEF files are ignored. Otherwise, they are read as sheets of metal by Magic. |
|
|
|
bool |
A flag to choose whether to include GDS pointers in the generated mag files or not. |
|
|
|
Path |
A path to the |
|
|
|
Path |
A path to a Magic tech file which, mainly, has DRC rules. |
|
|
|
Path |
A path to a PDK-specific setup file sourced by |
|
|
|
List[Path]? |
A list of pre-processed concrete views for cells. Read as a fallback for undefined cells. |
|
|
|
List[Path]? |
A list of pre-processed abstract LEF views for cells. Read as a fallback for undefined cells in scripts where cells are black-boxed. |
|
|
|
bool |
Capture errors print by Magic and quit when a fatal error is encountered. Fatal errors are determined heuristically. It is not guaranteed that they are fatal errors. Hence this is function is gated by a variable. This function is needed because Magic does not throw errors. |
|
|
|
bool |
Whether to prioritize GDS (if found) when running this step. |
|
SPICE Model Extraction¶
Extracts a SPICE netlist from the GDSII stream. Used in Layout vs. Schematic checks.
Also, the metrics will be updated with magic__illegal_overlap__count
. You can use
the relevant checker to quit if that number is
nonzero.
Importing
from openlane.steps.magic import SpiceExtraction
# or
from openlane.steps import Step
SpiceExtraction = Step.factory.get("Magic.SpiceExtraction")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
GDSII Stream (.gds) |
Simulation Program with Integrated Circuit Emphasis (.spice) |
Design Exchange Format (.def) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
A flag to choose whether labels are read with DEF files or not. From magic docs: “The ‘-labels’ option to the ‘def read’ command causes each net in the NETS and SPECIALNETS sections of the DEF file to be annotated with a label having the net name as the label text.” If LVS fails, try disabling this option. |
|
|
|
bool |
A flag to enable polygon subcells in magic for gds read potentially speeding up magic. From magic docs: “Put non-Manhattan polygons. This prevents interations with other polygons on the same plane and so reduces tile splitting.” |
|
|
|
bool |
If set to true, blockages in DEF files are ignored. Otherwise, they are read as sheets of metal by Magic. |
|
|
|
bool |
A flag to choose whether to include GDS pointers in the generated mag files or not. |
|
|
|
Path |
A path to the |
|
|
|
Path |
A path to a Magic tech file which, mainly, has DRC rules. |
|
|
|
Path |
A path to a PDK-specific setup file sourced by |
|
|
|
List[Path]? |
A list of pre-processed concrete views for cells. Read as a fallback for undefined cells. |
|
|
|
List[Path]? |
A list of pre-processed abstract LEF views for cells. Read as a fallback for undefined cells in scripts where cells are black-boxed. |
|
|
|
bool |
Capture errors print by Magic and quit when a fatal error is encountered. Fatal errors are determined heuristically. It is not guaranteed that they are fatal errors. Hence this is function is gated by a variable. This function is needed because Magic does not throw errors. |
|
|
|
bool |
A flag to choose whether to use GDS for spice extraction or not. If not, then the extraction will be done using the DEF/LEF, which is faster. |
|
|
|
List[str]? |
A list of regular experssions which are matched against the cells of a the design. Matches are abstracted (black-boxed) during SPICE extraction. |
|
|
|
bool |
Enables connections by label in LVS by skipping |
|
|
|
bool |
Enables adding resistors to shorts- resolves LVS issues if more than one top-level pin is connected to the same net, but may increase runtime and break some designs. Proceed with caution. |
|
|
|
bool |
Extracts a SPICE netlist based on black-boxed standard cells and macros (basically, anything with a LEF) rather than transistors. An error will be thrown if both this and |
|
GDSII Stream Out (Magic)¶
Converts DEF views into GDSII streams using Magic.
If PRIMARY_GDSII_STREAMOUT_TOOL
is set to "magic"
, both GDS and MAG_GDS
will be updated, and if set to another tool, only MAG_GDS
will be
updated.
Importing
from openlane.steps.magic import StreamOut
# or
from openlane.steps import Step
StreamOut = Step.factory.get("Magic.StreamOut")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
Design Exchange Format (.def) |
GDSII Stream (.gds) |
GDSII Stream (Magic) (.magic.gds) |
|
Magic VLSI View (.mag) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
A flag to choose whether labels are read with DEF files or not. From magic docs: “The ‘-labels’ option to the ‘def read’ command causes each net in the NETS and SPECIALNETS sections of the DEF file to be annotated with a label having the net name as the label text.” If LVS fails, try disabling this option. |
|
|
|
bool |
A flag to enable polygon subcells in magic for gds read potentially speeding up magic. From magic docs: “Put non-Manhattan polygons. This prevents interations with other polygons on the same plane and so reduces tile splitting.” |
|
|
|
bool |
If set to true, blockages in DEF files are ignored. Otherwise, they are read as sheets of metal by Magic. |
|
|
|
bool |
A flag to choose whether to include GDS pointers in the generated mag files or not. |
|
|
|
Path |
A path to the |
|
|
|
Path |
A path to a Magic tech file which, mainly, has DRC rules. |
|
|
|
Path |
A path to a PDK-specific setup file sourced by |
|
|
|
List[Path]? |
A list of pre-processed concrete views for cells. Read as a fallback for undefined cells. |
|
|
|
List[Path]? |
A list of pre-processed abstract LEF views for cells. Read as a fallback for undefined cells in scripts where cells are black-boxed. |
|
|
|
bool |
Capture errors print by Magic and quit when a fatal error is encountered. Fatal errors are determined heuristically. It is not guaranteed that they are fatal errors. Hence this is function is gated by a variable. This function is needed because Magic does not throw errors. |
|
|
|
Tuple[Decimal, Decimal, Decimal, Decimal]? |
Specific die area to be used in floorplanning when |
|
µm |
|
bool |
A flag to move the layout such that it’s origin in the lef generated by magic is 0,0. |
|
|
|
bool |
A flag to disable writing Caltech Intermediate Format (CIF) hierarchy and subcell array information to the GDSII file. |
|
|
|
‘PDK’| |
If set to PDK, magic will use the PDK definition of the STD cells for macros inside the design. Otherwise, the macro is completely treated as a blackbox and magic will use the existing cell definition inside the macro gds. This mode is only supported for macros specified in MACROS variable |
|
Write LEF (Magic)¶
Writes a LEF view of the design using the GDS using Magic.
Importing
from openlane.steps.magic import WriteLEF
# or
from openlane.steps import Step
WriteLEF = Step.factory.get("Magic.WriteLEF")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
GDSII Stream (.gds) |
Library Exchange Format (.lef) |
Design Exchange Format (.def) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
A flag to choose whether labels are read with DEF files or not. From magic docs: “The ‘-labels’ option to the ‘def read’ command causes each net in the NETS and SPECIALNETS sections of the DEF file to be annotated with a label having the net name as the label text.” If LVS fails, try disabling this option. |
|
|
|
bool |
A flag to enable polygon subcells in magic for gds read potentially speeding up magic. From magic docs: “Put non-Manhattan polygons. This prevents interations with other polygons on the same plane and so reduces tile splitting.” |
|
|
|
bool |
If set to true, blockages in DEF files are ignored. Otherwise, they are read as sheets of metal by Magic. |
|
|
|
bool |
A flag to choose whether to include GDS pointers in the generated mag files or not. |
|
|
|
Path |
A path to the |
|
|
|
Path |
A path to a Magic tech file which, mainly, has DRC rules. |
|
|
|
Path |
A path to a PDK-specific setup file sourced by |
|
|
|
List[Path]? |
A list of pre-processed concrete views for cells. Read as a fallback for undefined cells. |
|
|
|
List[Path]? |
A list of pre-processed abstract LEF views for cells. Read as a fallback for undefined cells in scripts where cells are black-boxed. |
|
|
|
bool |
Capture errors print by Magic and quit when a fatal error is encountered. Fatal errors are determined heuristically. It is not guaranteed that they are fatal errors. Hence this is function is gated by a variable. This function is needed because Magic does not throw errors. |
|
|
|
bool |
A flag to choose whether to use GDS for LEF writing. If not, then the extraction will be done using abstract LEF views. |
|
|
|
bool |
A flag to specify whether or not the output LEF should include all shapes inside the macro or an abstracted view of the macro LEF view via magic. |
|
|
|
bool |
If true, the LEF write will mark only areas that are port labels as pins, while marking the rest of each related net as an obstruction. Otherwise, the labeled port and the any connected metal on the same layer are marked as a pin. |
|
Netgen¶
Netgen LVS¶
Performs Layout vs. Schematic checks on the extracted SPICE netlist versus. a Verilog netlist with power connections.
This verifies the following: * There are no unexpected shorts in the final layout. * There are no unexpected opens in the final layout. * All signals are connected correctly.
Importing
from openlane.steps.netgen import LVS
# or
from openlane.steps import Step
LVS = Step.factory.get("Netgen.LVS")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
Simulation Program with Integrated Circuit Emphasis (.spice) |
|
Powered Verilog Netlist (.pnl.v) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
A flag to choose whether to use GDS for spice extraction or not. If not, then the extraction will be done using the DEF/LEF, which is faster. |
|
|
|
Path |
A path to the setup file for Netgen used to configure LVS. If set to None, this PDK will not support Netgen-based steps. |
|
|
|
bool |
A flag that enables including the gate-level netlist of macros while running Netgen |
|
|
|
List[str]? |
A list of cell names to be flattened while running LVS |
|
Odb¶
Add PDN obstructions¶
Importing
from openlane.steps.odb import AddPDNObstructions
# or
from openlane.steps import Step
AddPDNObstructions = Step.factory.get("Odb.AddPDNObstructions")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
List[str]? |
Add routing obstructions to the design before PDN stage. If set to |
|
µm |
Add Obstructions¶
Importing
from openlane.steps.odb import AddRoutingObstructions
# or
from openlane.steps import Step
AddRoutingObstructions = Step.factory.get("Odb.AddRoutingObstructions")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
List[str]? |
Add routing obstructions to the design. If set to |
|
µm |
Apply DEF Template¶
Copies the floorplan of a “template” DEF file for a new design, i.e., it will copy the die area, core area, and non-power pin names and locations.
Importing
from openlane.steps.odb import ApplyDEFTemplate
# or
from openlane.steps import Step
ApplyDEFTemplate = Step.factory.get("Odb.ApplyDEFTemplate")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
‘strict’| |
Whether to require that the pin set of the DEF template and the design should be identical. In permissive mode, pins that are in the design and not in the template will be excluded, and vice versa. |
|
|
|
bool |
Whether to always copy all power pins from the DEF template to the design. |
|
Generate Cell Frequency Tables¶
Creates a number of tables to show the cell frequencies by:
Cells
Buffer cells only
Cell Function*
Standard Cell Library*
These tables only return meaningful info with PDKs distributed in the Open_PDKs format, i.e., all cells are named
{scl}__{cell_fn}_{size}
.
Importing
from openlane.steps.odb import CellFrequencyTables
# or
from openlane.steps import Step
CellFrequencyTables = Step.factory.get("Odb.CellFrequencyTables")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
Check Antenna Properties of Pins in The Generated Design LEF view¶
Importing
from openlane.steps.odb import CheckDesignAntennaProperties
# or
from openlane.steps import Step
CheckDesignAntennaProperties = Step.factory.get("Odb.CheckDesignAntennaProperties")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
|
Library Exchange Format (.lef) |
Check Antenna Properties of Macros Pins in Their LEF Views¶
Importing
from openlane.steps.odb import CheckMacroAntennaProperties
# or
from openlane.steps import Step
CheckMacroAntennaProperties = Step.factory.get("Odb.CheckMacroAntennaProperties")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
Custom I/O Pin Placement Script¶
Places I/O pins using a custom script, which uses a “pin order configuration” file.
Check the reference documentation for the structure of said file.
Importing
from openlane.steps.odb import CustomIOPlacement
# or
from openlane.steps import Step
CustomIOPlacement = Step.factory.get("Odb.CustomIOPlacement")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
Decimal |
Extends the vertical io pins outside of the die by the specified units. |
|
µm |
|
Decimal |
Extends the horizontal io pins outside of the die by the specified units. |
|
µm |
|
Decimal |
A multiplier for vertical pin thickness. Base thickness is the pins layer min width. |
|
|
|
Decimal |
A multiplier for horizontal pin thickness. Base thickness is the pins layer min width. |
|
|
|
Decimal? |
|
|
µm |
|
Decimal? |
|
|
µm |
|
Path? |
Path to the configuration file. If set to |
|
|
|
‘none’| |
Controls whether to emit an error in: no situation, when pins exist in the design that do not exist in the config file, when pins exist in the config file that do not exist in the design, and both respectively. |
|
Diodes on Ports Protection Routine¶
Unconditionally inserts diodes on design ports diodes on ports, to mitigate the antenna effect.
Useful for hardening macros, where ports may get long wires that are unaccounted for when hardening a top-level chip.
The placement is legalized by performing detailed placement and global routing after inserting the diodes.
Prior to beta 16, this step did not legalize its placement: if you would
like to retain the old behavior without legalization, try
Odb.PortDiodePlacement
.
Importing
from openlane.steps.odb import DiodesOnPorts
# or
from openlane.steps import Step
DiodesOnPorts = Step.factory.get("Odb.DiodesOnPorts")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
Design Exchange Format (.def) |
OpenDB Database (.odb) |
|
Powered Verilog Netlist (.pnl.v) |
|
Verilog Netlist (.nl.v) |
|
Design Constraints (.sdc) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
‘none’| |
Always insert diodes on ports with the specified polarities. |
|
|
|
Decimal |
Cell padding value (in sites) for global placement. Used by this step only to emit a warning if it’s 0. |
|
sites |
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
bool |
Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design. |
|
|
|
Decimal |
Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement. |
|
µm |
|
Decimal |
Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement. |
|
µm |
|
Decimal |
Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement. |
|
sites |
|
str? |
The name of lowest layer to be used in routing the clock net. |
|
|
|
str? |
The name of highest layer to be used in routing the clock net. |
|
|
|
Decimal |
Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction. |
|
|
|
int |
Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches. |
|
|
|
List[Decimal] |
Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1. |
|
|
|
int? |
Diode cell padding; increases the width of diode cells during placement checks.. |
|
sites |
|
bool |
Allow congestion during global routing |
|
|
|
int |
The maximum number of iterations for global antenna repairs. |
|
|
|
int |
The maximum number of iterations waiting for the overflow to reach the desired value. |
|
|
|
int |
The margin to over fix antenna violations. |
|
% |
Fuzzy Diode Placement¶
Runs a custom diode placement script to mitigate the antenna effect.
This script uses the Manhattan length of a (non-existent) wire at the global placement stage, and places diodes if they exceed a certain threshold. This, however, requires some padding: GPL_CELL_PADDING and DPL_CELL_PADDING must be higher than 0 for this script to work reliably.
The placement is not legalized.
The original script was written by Sylvain “tnt” Munaut.
Importing
from openlane.steps.odb import FuzzyDiodePlacement
# or
from openlane.steps import Step
FuzzyDiodePlacement = Step.factory.get("Odb.FuzzyDiodePlacement")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
Decimal |
A Manhattan distance above which a diode is recommended to be inserted by the heuristic inserter. If not specified, the heuristic algorithm. |
|
µm |
|
Decimal |
Cell padding value (in sites) for global placement. Used by this step only to emit a warning if it’s 0. |
|
sites |
Heuristic Diode Insertion Routine¶
Runs a custom diode insertion routine to mitigate the antenna effect.
This script uses the Manhattan length of a (non-existent) wire at the global placement stage, and places diodes if they exceed a certain threshold. This, however, requires some padding: GPL_CELL_PADDING and DPL_CELL_PADDING must be higher than 0 for this script to work reliably.
The placement is then legalized by performing detailed placement and global routing after inserting the diodes.
The original script was written by Sylvain “tnt” Munaut.
Prior to beta 16, this step did not legalize its placement: if you would
like to retain the old behavior without legalization, try
Odb.FuzzyDiodePlacement
.
Importing
from openlane.steps.odb import HeuristicDiodeInsertion
# or
from openlane.steps import Step
HeuristicDiodeInsertion = Step.factory.get("Odb.HeuristicDiodeInsertion")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
Design Exchange Format (.def) |
OpenDB Database (.odb) |
|
Powered Verilog Netlist (.pnl.v) |
|
Verilog Netlist (.nl.v) |
|
Design Constraints (.sdc) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
Decimal |
A Manhattan distance above which a diode is recommended to be inserted by the heuristic inserter. If not specified, the heuristic algorithm. |
|
µm |
|
Decimal |
Cell padding value (in sites) for global placement. Used by this step only to emit a warning if it’s 0. |
|
sites |
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
bool |
Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design. |
|
|
|
Decimal |
Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement. |
|
µm |
|
Decimal |
Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement. |
|
µm |
|
Decimal |
Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement. |
|
sites |
|
str? |
The name of lowest layer to be used in routing the clock net. |
|
|
|
str? |
The name of highest layer to be used in routing the clock net. |
|
|
|
Decimal |
Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction. |
|
|
|
int |
Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches. |
|
|
|
List[Decimal] |
Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1. |
|
|
|
int? |
Diode cell padding; increases the width of diode cells during placement checks.. |
|
sites |
|
bool |
Allow congestion during global routing |
|
|
|
int |
The maximum number of iterations for global antenna repairs. |
|
|
|
int |
The maximum number of iterations waiting for the overflow to reach the desired value. |
|
|
|
int |
The margin to over fix antenna violations. |
|
% |
Manual Global Placement¶
This is an step to override the placement of one or more instances at user-specified locations.
Alternatively, if this is a custom design with a few cells, this can be used in place of the global placement entirely.
Importing
from openlane.steps.odb import ManualGlobalPlacement
# or
from openlane.steps import Step
ManualGlobalPlacement = Step.factory.get("Odb.ManualGlobalPlacement")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
Dict[str, Instance]? |
A dictionary of instances to their global (non-legalized and unfixed) placement location. |
|
Manual Macro Placement¶
Performs macro placement using a simple configuration file. The file is
defined as a line-break delimited list of instances and positions, in the
format instance_name X_pos Y_pos Orientation
.
If no macro instances are configured, this step is skipped.
Importing
from openlane.steps.odb import ManualMacroPlacement
# or
from openlane.steps import Step
ManualMacroPlacement = Step.factory.get("Odb.ManualMacroPlacement")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
Path? |
Path to an optional override for instance placement instead of the |
|
Port Diode Placement Script¶
Unconditionally inserts diodes on design ports diodes on ports, to mitigate the antenna effect.
Useful for hardening macros, where ports may get long wires that are unaccounted for when hardening a top-level chip.
The placement is not legalized.
Importing
from openlane.steps.odb import PortDiodePlacement
# or
from openlane.steps import Step
PortDiodePlacement = Step.factory.get("Odb.PortDiodePlacement")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
‘none’| |
Always insert diodes on ports with the specified polarities. |
|
|
|
Decimal |
Cell padding value (in sites) for global placement. Used by this step only to emit a warning if it’s 0. |
|
sites |
Remove PDN obstructions¶
Importing
from openlane.steps.odb import RemovePDNObstructions
# or
from openlane.steps import Step
RemovePDNObstructions = Step.factory.get("Odb.RemovePDNObstructions")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
List[str]? |
Add routing obstructions to the design before PDN stage. If set to |
|
µm |
Remove Obstructions¶
Importing
from openlane.steps.odb import RemoveRoutingObstructions
# or
from openlane.steps import Step
RemoveRoutingObstructions = Step.factory.get("Odb.RemoveRoutingObstructions")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
List[str]? |
Add routing obstructions to the design. If set to |
|
µm |
Report Disconnected Pins¶
Creates a table of disconnected pins in the design, updating metrics as appropriate.
Disconnected pins may be marked “critical” if they are very likely to result in a dead design. We determine if a pin is critical as follows:
For the top-level macro: for these four kinds of pins: inputs, outputs, power inouts, and ground inouts, at least one of each kind must be connected or else all pins of a certain kind are counted as critical disconnected pins.
- For instances:
Any unconnected input is a critical disconnected pin.
If there isn’t at least one output connected, all disconnected outputs are critical disconnected pins.
Any disconnected power inout pins are critical disconnected pins.
The metrics design__disconnected_pin__count
and
design__critical_disconnected_pin__count
is updated. It is recommended
to use the checker Checker.DisconnectedPins
to check that there are
no critical disconnected pins.
Importing
from openlane.steps.odb import ReportDisconnectedPins
# or
from openlane.steps import Step
ReportDisconnectedPins = Step.factory.get("Odb.ReportDisconnectedPins")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
List[str]? |
Modules (or cells) to ignore when checking for disconnected pins. |
|
Report Wire Length¶
Outputs a CSV of long wires, printed by length. Useful as a design aid to detect when one wire is connected to too many things.
Importing
from openlane.steps.odb import ReportWireLength
# or
from openlane.steps import Step
ReportWireLength = Step.factory.get("Odb.ReportWireLength")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
Set Power Connections¶
Uses JSON netlist and module information in Odb to add global power connections for macros at the top level of a design.
If the JSON netlist is hierarchical (e.g. by using a keep hierarchy attribute) this Step emits a warning and does not attempt to connect any macros instantiated within submodules.
Importing
from openlane.steps.odb import SetPowerConnections
# or
from openlane.steps import Step
SetPowerConnections = Step.factory.get("Odb.SetPowerConnections")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
Design JSON Header File (.h.json) |
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
Write Verilog Header¶
Writes a Verilog header of the module using information from the generated
PDN, guarded by the value of VERILOG_POWER_DEFINE
, and the JSON header.
Importing
from openlane.steps.odb import WriteVerilogHeader
# or
from openlane.steps import Step
WriteVerilogHeader = Step.factory.get("Odb.WriteVerilogHeader")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
Verilog Header (.vh) |
Design JSON Header File (.h.json) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
str? |
Specifies the name of the define used to guard power and ground connections in the output Verilog header. |
|
OpenROAD¶
Basic Macro Placement¶
Importing
from openlane.steps.openroad import BasicMacroPlacement
# or
from openlane.steps import Step
BasicMacroPlacement = Step.factory.get("OpenROAD.BasicMacroPlacement")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
|
Design Constraints (.sdc) |
|
Verilog Netlist (.nl.v) |
|
Powered Verilog Netlist (.pnl.v) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
str |
Macro placement halo. Format: |
|
µm |
|
str |
Channel widths between macros. Format: |
|
µm |
Clock Tree Synthesis¶
Creates a Clock tree for an ODB file with detailed-placed cells, using reasonably accurate resistance and capacitance estimations. Detailed Placement is then re-performed to accommodate the new cells.
Importing
from openlane.steps.openroad import CTS
# or
from openlane.steps import Step
CTS = Step.factory.get("OpenROAD.CTS")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
|
Design Constraints (.sdc) |
|
Verilog Netlist (.nl.v) |
|
Powered Verilog Netlist (.pnl.v) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
bool |
Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design. |
|
|
|
Decimal |
Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement. |
|
µm |
|
Decimal |
Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement. |
|
µm |
|
Decimal |
Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement. |
|
sites |
|
int |
Specifies the maximum number of sinks per cluster. |
|
|
|
Decimal |
Specifies maximum diameter of the sink cluster. |
|
µm |
|
Decimal |
Specifies the maximum wire length on the clock net. |
|
µm |
|
bool |
Specifies whether or not to disable post cts processing for outlier sinks. |
|
|
|
Decimal |
Specifies the distance between buffers when creating the clock tree. |
|
µm |
|
List[str]? |
A list of fully-qualified IPVT corners to use during clock tree synthesis. If unspecified, the value for |
|
|
|
str |
Defines the cell inserted at the root of the clock tree. Used in CTS. |
|
|
|
List[str] |
Defines the list of clock buffers to be used in CTS. |
|
|
|
Decimal? |
Overrides the maximum capacitance CTS characterization will test. If omitted, the capacitance is extracted from the lib information of the buffers in CTS_CLK_BUFFERS. |
|
pF |
|
Decimal? |
Overrides the maximum transition time CTS characterization will test. If omitted, the slew is extracted from the lib information of the buffers in CTS_CLK_BUFFERS. |
|
ns |
Check Antennas¶
Runs OpenROAD to check if one or more long nets may constitute an antenna risk.
The metric route__antenna_violation__count
will be updated with the number of violating nets.
Importing
from openlane.steps.openroad import CheckAntennas
# or
from openlane.steps import Step
CheckAntennas = Step.factory.get("OpenROAD.CheckAntennas")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
Check Macro Instances¶
Checks if all macro instances declared in the configuration are, in fact, in the design, emitting an error otherwise.
Nested macros (macros within macros) are supported provided netlist views are available for the macro.
Importing
from openlane.steps.openroad import CheckMacroInstances
# or
from openlane.steps import Step
CheckMacroInstances = Step.factory.get("OpenROAD.CheckMacroInstances")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
Verilog Netlist (.nl.v) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
Check SDC Files¶
Checks that the two variables used for SDC files by OpenROAD steps,
namely, PNR_SDC_FILE
and SIGNOFF_SDC_FILE
, are explicitly set to
valid paths by the users, and emits a warning that the fallback will be
utilized otherwise.
Importing
from openlane.steps.openroad import CheckSDCFiles
# or
from openlane.steps import Step
CheckSDCFiles = Step.factory.get("OpenROAD.CheckSDCFiles")
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Specifies the SDC file for STA during signoff |
|
Cut Rows¶
Cut floorplan rows with respect to placed macros.
Importing
from openlane.steps.openroad import CutRows
# or
from openlane.steps import Step
CutRows = Step.factory.get("OpenROAD.CutRows")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
Decimal |
Specify the horizontal halo size around macros while cutting rows. |
|
µm |
|
Decimal |
Specify the vertical halo size around macros while cutting rows. |
|
µm |
DEF to OpenDB¶
Converts a DEF view to an ODB view.
Useful if you have a custom step that manipulates the layout outside of OpenROAD, but you would like to update the OpenROAD database.
Importing
from openlane.steps.openroad import DEFtoODB
# or
from openlane.steps import Step
DEFtoODB = Step.factory.get("OpenROAD.DEFtoODB")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
Design Exchange Format (.def) |
OpenDB Database (.odb) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
Detailed Placement¶
Performs “detailed placement” on an ODB file with global placement. This results in a concrete and legal placement of all cells.
Importing
from openlane.steps.openroad import DetailedPlacement
# or
from openlane.steps import Step
DetailedPlacement = Step.factory.get("OpenROAD.DetailedPlacement")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
|
Design Constraints (.sdc) |
|
Verilog Netlist (.nl.v) |
|
Powered Verilog Netlist (.pnl.v) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
bool |
Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design. |
|
|
|
Decimal |
Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement. |
|
µm |
|
Decimal |
Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement. |
|
µm |
|
Decimal |
Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement. |
|
sites |
Detailed Routing¶
The latter phase of routing. This transforms the abstract nets from global routing into wires on the metal layers that respect all design rules, avoids creating accidental shorts, and ensures all wires are connected.
This is by far the longest part of a typical flow, taking hours, days or weeks on larger designs.
After this point, all cells connected to a net can no longer be moved or removed without a custom-written step of some kind that will also rip up wires.
Importing
from openlane.steps.openroad import DetailedRouting
# or
from openlane.steps import Step
DetailedRouting = Step.factory.get("OpenROAD.DetailedRouting")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
|
Design Constraints (.sdc) |
|
Verilog Netlist (.nl.v) |
|
Powered Verilog Netlist (.pnl.v) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
int? |
Specifies the number of threads to be used in OpenROAD Detailed Routing. If unset, this will be equal to your machine’s thread count. |
|
|
|
str? |
An optional override to the lowest layer used in detailed routing. For example, in sky130, you may want global routing to avoid li1, but let detailed routing use li1 if it has to. |
|
|
|
str? |
An optional override to the highest layer used in detailed routing. |
|
|
|
int |
Specifies the maximum number of optimization iterations during Detailed Routing in TritonRoute. |
|
Fill Insertion¶
Fills gaps in the floorplan with filler and decap cells.
This is run after detailed placement. After this point, the design is basically completely hardened.
Importing
from openlane.steps.openroad import FillInsertion
# or
from openlane.steps import Step
FillInsertion = Step.factory.get("OpenROAD.FillInsertion")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
|
Design Constraints (.sdc) |
|
Verilog Netlist (.nl.v) |
|
Powered Verilog Netlist (.pnl.v) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
Floorplan Initialization¶
Creates DEF and ODB files with the initial floorplan based on the Yosys netlist.
Importing
from openlane.steps.openroad import Floorplan
# or
from openlane.steps import Step
Floorplan = Step.factory.get("OpenROAD.Floorplan")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
Verilog Netlist (.nl.v) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
|
Design Constraints (.sdc) |
|
Verilog Netlist (.nl.v) |
|
Powered Verilog Netlist (.pnl.v) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
‘absolute’| |
Sizing mode for floorplanning |
|
|
|
Decimal |
The core’s aspect ratio (height / width). |
|
|
|
Decimal |
The core utilization percentage. |
|
% |
|
List[Tuple[Decimal, Decimal, Decimal, Decimal]]? |
Obstructions applied at floorplanning stage. Placement sites are never generated at these locations, which guarantees that it will remain empty throughout the entire flow. |
|
µm |
|
List[Tuple[Decimal, Decimal, Decimal, Decimal]]? |
Soft placement blockages applied at the floorplanning stage. Areas that are soft-blocked will not be used by the initial placer, however, later phases such as buffer insertion or clock tree synthesis are still allowed to place cells in this area. |
|
µm |
|
Tuple[Decimal, Decimal, Decimal, Decimal]? |
Specifies a core area (i.e. die area minus margins) to be used in floorplanning. It must be paired with |
|
µm |
|
Decimal |
The core margin, in multiples of site heights, from the bottom boundary. If |
|
|
|
Decimal |
The core margin, in multiples of site heights, from the top boundary. If |
|
|
|
Decimal |
The core margin, in multiples of site widths, from the left boundary. If |
|
|
|
Decimal |
The core margin, in multiples of site widths, from the right boundary. If |
|
|
|
List[str]? |
Explicitly specify sites other than |
|
Power Distribution Network Generation¶
Creates a power distribution network on a floorplanned ODB file.
Importing
from openlane.steps.openroad import GeneratePDN
# or
from openlane.steps import Step
GeneratePDN = Step.factory.get("OpenROAD.GeneratePDN")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
|
Design Constraints (.sdc) |
|
Verilog Netlist (.nl.v) |
|
Powered Verilog Netlist (.pnl.v) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
bool |
Enables |
|
|
|
bool |
Enables adding a core ring around the design. More details on the control variables in the PDK config documentation. |
|
|
|
bool |
Enables the creation of rails in the power grid. |
|
|
|
Decimal |
Sets the horizontal halo around the macros during power grid insertion. |
|
µm |
|
Decimal |
Sets the vertical halo around the macros during power grid insertion. |
|
µm |
|
bool |
Controls the layers used in the power grid. If set to false, only the lower layer will be used, which is useful when hardening a macro for integrating into a larger top-level design. |
|
|
|
Decimal |
The offset for the power distribution network rails for first metal layer. |
|
µm |
|
Decimal |
The strap width for the vertical layer in generated power distribution networks. |
|
µm |
|
Decimal |
The strap width for the horizontal layer in generated power distribution networks. |
|
µm |
|
Decimal |
Intra-spacing (within a set) of vertical straps in generated power distribution networks. |
|
µm |
|
Decimal |
Intra-spacing (within a set) of horizontal straps in generated power distribution networks. |
|
µm |
|
Decimal |
Inter-distance (between sets) of vertical power straps in generated power distribution networks. |
|
µm |
|
Decimal |
Inter-distance (between sets) of horizontal power straps in generated power distribution networks. |
|
µm |
|
Decimal |
Initial offset for sets of vertical power straps. |
|
µm |
|
Decimal |
Initial offset for sets of horizontal power straps. |
|
µm |
|
Decimal |
The width for the vertical layer in the core ring of generated power distribution networks. |
|
µm |
|
Decimal |
The width for the horizontal layer in the core ring of generated power distribution networks. |
|
µm |
|
Decimal |
The spacing for the vertical layer in the core ring of generated power distribution networks. |
|
µm |
|
Decimal |
The spacing for the horizontal layer in the core ring of generated power distribution networks. |
|
µm |
|
Decimal |
The offset for the vertical layer in the core ring of generated power distribution networks. |
|
µm |
|
Decimal |
The offset for the horizontal layer in the core ring of generated power distribution networks. |
|
µm |
|
str |
Defines the metal layer used for PDN rails. |
|
|
|
Decimal |
Defines the width of PDN rails on the |
|
µm |
|
str |
Defines the horizontal PDN layer. |
|
|
|
str |
Defines the vertical PDN layer. |
|
|
|
Path? |
A custom PDN configuration file. If not provided, the default PDN config will be used. |
|
Global Placement¶
Performs a somewhat nebulous initial placement for standard cells in a floorplan. While the placement is not concrete, it is enough to start accounting for issues such as fanout, transition time, et cetera.
Importing
from openlane.steps.openroad import GlobalPlacement
# or
from openlane.steps import Step
GlobalPlacement = Step.factory.get("OpenROAD.GlobalPlacement")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
|
Design Constraints (.sdc) |
|
Verilog Netlist (.nl.v) |
|
Powered Verilog Netlist (.pnl.v) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
str? |
The name of lowest layer to be used in routing the clock net. |
|
|
|
str? |
The name of highest layer to be used in routing the clock net. |
|
|
|
Decimal |
Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction. |
|
|
|
int |
Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches. |
|
|
|
List[Decimal] |
Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1. |
|
|
|
Decimal? |
The desired placement density of cells. If not specified, the value will be equal to ( |
|
% |
|
bool |
Specifies whether the placer should run initial placement or not. |
|
|
|
Decimal |
Global placement initial wirelength coefficient. Decreasing the variable will modify the initial placement of the standard cells to reduce the wirelengths |
|
|
|
Decimal? |
Sets a lower bound on the µ_k variable in the GPL algorithm. Useful if global placement diverges. See https://openroad.readthedocs.io/en/latest/main/src/gpl/README.html |
|
|
|
Decimal? |
Sets a upper bound on the µ_k variable in the GPL algorithm. Useful if global placement diverges.See https://openroad.readthedocs.io/en/latest/main/src/gpl/README.html |
|
|
|
Decimal |
The core utilization percentage. |
|
% |
|
Decimal |
Cell padding value (in sites) for global placement. The number will be integer divided by 2 and placed on both sides. |
|
sites |
|
bool |
Specifies whether the placer should use time driven placement. |
|
|
|
bool |
Specifies whether the placer should use routability driven placement. |
|
|
|
Decimal? |
Sets overflow threshold for routability mode. |
|
Global Placement Skip IO¶
Performs global placement without taking I/O into consideration.
This is useful for flows where the: * Cells are placed * I/Os are placed to match the cells * Cells are then re-placed for an optimal placement
Importing
from openlane.steps.openroad import GlobalPlacementSkipIO
# or
from openlane.steps import Step
GlobalPlacementSkipIO = Step.factory.get("OpenROAD.GlobalPlacementSkipIO")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
|
Design Constraints (.sdc) |
|
Verilog Netlist (.nl.v) |
|
Powered Verilog Netlist (.pnl.v) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
str? |
The name of lowest layer to be used in routing the clock net. |
|
|
|
str? |
The name of highest layer to be used in routing the clock net. |
|
|
|
Decimal |
Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction. |
|
|
|
int |
Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches. |
|
|
|
List[Decimal] |
Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1. |
|
|
|
Decimal? |
The desired placement density of cells. If not specified, the value will be equal to ( |
|
% |
|
bool |
Specifies whether the placer should run initial placement or not. |
|
|
|
Decimal |
Global placement initial wirelength coefficient. Decreasing the variable will modify the initial placement of the standard cells to reduce the wirelengths |
|
|
|
Decimal? |
Sets a lower bound on the µ_k variable in the GPL algorithm. Useful if global placement diverges. See https://openroad.readthedocs.io/en/latest/main/src/gpl/README.html |
|
|
|
Decimal? |
Sets a upper bound on the µ_k variable in the GPL algorithm. Useful if global placement diverges.See https://openroad.readthedocs.io/en/latest/main/src/gpl/README.html |
|
|
|
Decimal |
The core utilization percentage. |
|
% |
|
Decimal |
Cell padding value (in sites) for global placement. The number will be integer divided by 2 and placed on both sides. |
|
sites |
|
‘matching’| |
Decides the mode of the random IO placement option. |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
Global Routing¶
The initial phase of routing. Given a detailed-placed ODB file, this phase starts assigning coarse-grained routing “regions” for each net so they may be later connected to wires.
Estimated capacitance and resistance values are much more accurate for global routing.
Importing
from openlane.steps.openroad import GlobalRouting
# or
from openlane.steps import Step
GlobalRouting = Step.factory.get("OpenROAD.GlobalRouting")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
str? |
The name of lowest layer to be used in routing the clock net. |
|
|
|
str? |
The name of highest layer to be used in routing the clock net. |
|
|
|
Decimal |
Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction. |
|
|
|
int |
Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches. |
|
|
|
List[Decimal] |
Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1. |
|
|
|
int? |
Diode cell padding; increases the width of diode cells during placement checks.. |
|
sites |
|
bool |
Allow congestion during global routing |
|
|
|
int |
The maximum number of iterations for global antenna repairs. |
|
|
|
int |
The maximum number of iterations waiting for the overflow to reach the desired value. |
|
|
|
int |
The margin to over fix antenna violations. |
|
% |
|
bool |
Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design. |
|
|
|
Decimal |
Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement. |
|
µm |
|
Decimal |
Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement. |
|
µm |
|
Decimal |
Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement. |
|
sites |
I/O Placement¶
Places I/O pins on a floor-planned ODB file using OpenROAD’s built-in placer.
If FP_PIN_ORDER_CFG
is not None
, this step is skipped (for
compatibility with OpenLane 1.)
Importing
from openlane.steps.openroad import IOPlacement
# or
from openlane.steps import Step
IOPlacement = Step.factory.get("OpenROAD.IOPlacement")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
|
Design Constraints (.sdc) |
|
Verilog Netlist (.nl.v) |
|
Powered Verilog Netlist (.pnl.v) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
Decimal |
Extends the vertical io pins outside of the die by the specified units. |
|
µm |
|
Decimal |
Extends the horizontal io pins outside of the die by the specified units. |
|
µm |
|
Decimal |
A multiplier for vertical pin thickness. Base thickness is the pins layer min width. |
|
|
|
Decimal |
A multiplier for horizontal pin thickness. Base thickness is the pins layer min width. |
|
|
|
‘matching’| |
Decides the mode of the random IO placement option. |
|
|
|
Decimal? |
The minimum distance between two pins. If unspecified by a PDK, OpenROAD will use the length of two routing tracks. |
|
µm |
|
Path? |
Path to a custom pin configuration file. |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
Decimal? |
|
|
µm |
|
Decimal? |
|
|
µm |
Generate IR Drop Report¶
Performs static IR-drop analysis on the power distribution network. For power nets, this constitutes a decrease in voltage, and for ground nets, it constitutes an increase in voltage.
Importing
from openlane.steps.openroad import IRDropReport
# or
from openlane.steps import Step
IRDropReport = Step.factory.get("OpenROAD.IRDropReport")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
|
Standard Parasitics Extraction Format (.spef) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
Dict[str, Path]? |
Map of power and ground nets to OpenROAD PSM location files. See this for more info. |
|
Layout Static Timing Analysis¶
Performs Static Timing Analysis using OpenROAD on the ODB layout in its current state.
Importing
from openlane.steps.openroad import LayoutSTA
# or
from openlane.steps import Step
LayoutSTA = Step.factory.get("OpenROAD.LayoutSTA")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
Open In GUI¶
Opens the ODB view in the OpenROAD GUI. Useful to inspect some parameters, such as routing density and whatnot.
Importing
from openlane.steps.openroad import OpenGUI
# or
from openlane.steps import Step
OpenGUI = Step.factory.get("OpenROAD.OpenGUI")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
Parasitic Resistance/Capacitance Extraction¶
This extracts parasitic electrical values from a detailed-placed circuit. These can be used to create basically the highest accurate STA possible for a given design.
Importing
from openlane.steps.openroad import RCX
# or
from openlane.steps import Step
RCX = Step.factory.get("OpenROAD.RCX")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
Design Exchange Format (.def) |
Standard Parasitics Extraction Format (.spef) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
bool |
If enabled, the via and wire resistances will be merged. |
|
|
|
Path? |
Specifies SDC file to be used for RCX-based STA, which can be different from the one used for implementation. |
|
|
|
Dict[str, Path] |
Map of corner patterns to OpenRCX extraction rules. |
|
|
|
int? |
The maximum number of STA corners to run in parallel. If unset, this will be equal to your machine’s thread count. |
|
Antenna Repair¶
Applies antenna effect mitigations using global-routing information, then re-runs detailed placement and global routing to legalize any inserted diodes.
An antenna check is once again performed, updating the
route__antenna_violation__count
metric.
Importing
from openlane.steps.openroad import RepairAntennas
# or
from openlane.steps import Step
RepairAntennas = Step.factory.get("OpenROAD.RepairAntennas")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
str? |
The name of lowest layer to be used in routing the clock net. |
|
|
|
str? |
The name of highest layer to be used in routing the clock net. |
|
|
|
Decimal |
Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction. |
|
|
|
int |
Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches. |
|
|
|
List[Decimal] |
Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1. |
|
|
|
int? |
Diode cell padding; increases the width of diode cells during placement checks.. |
|
sites |
|
bool |
Allow congestion during global routing |
|
|
|
int |
The maximum number of iterations for global antenna repairs. |
|
|
|
int |
The maximum number of iterations waiting for the overflow to reach the desired value. |
|
|
|
int |
The margin to over fix antenna violations. |
|
% |
|
bool |
Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design. |
|
|
|
Decimal |
Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement. |
|
µm |
|
Decimal |
Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement. |
|
µm |
|
Decimal |
Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement. |
|
sites |
Repair Design (Post-Global Placement)¶
This is identical to OpenROAD.RepairDesignPostGPL. It is retained for backwards compatibility.
Importing
from openlane.steps.openroad import RepairDesign
# or
from openlane.steps import Step
RepairDesign = Step.factory.get("OpenROAD.RepairDesign")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
|
Design Constraints (.sdc) |
|
Verilog Netlist (.nl.v) |
|
Powered Verilog Netlist (.pnl.v) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
str? |
The name of lowest layer to be used in routing the clock net. |
|
|
|
str? |
The name of highest layer to be used in routing the clock net. |
|
|
|
Decimal |
Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction. |
|
|
|
int |
Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches. |
|
|
|
List[Decimal] |
Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1. |
|
|
|
int? |
Diode cell padding; increases the width of diode cells during placement checks.. |
|
sites |
|
bool |
Allow congestion during global routing |
|
|
|
int |
The maximum number of iterations for global antenna repairs. |
|
|
|
int |
The maximum number of iterations waiting for the overflow to reach the desired value. |
|
|
|
int |
The margin to over fix antenna violations. |
|
% |
|
bool |
Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design. |
|
|
|
Decimal |
Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement. |
|
µm |
|
Decimal |
Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement. |
|
µm |
|
Decimal |
Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement. |
|
sites |
|
str |
A single regular expression designating nets or instances as “don’t touch” by design repairs or resizer optimizations. |
|
|
|
List[str]? |
A list of nets and instances as “don’t touch” by design repairs or resizer optimizations. |
|
|
|
List[str]? |
A list of fully-qualified IPVT corners to use during resizer optimizations. If unspecified, the value for |
|
|
|
bool |
Specifies whether or not to insert buffers on input ports when design repairs are run. |
|
|
|
bool |
Specifies whether or not to insert buffers on input ports when design repairs are run. |
|
|
|
bool |
Specifies whether or not to repair tie cells fanout when design repairs are run. |
|
|
|
bool |
Allows tie separation when performing design repairs. |
|
|
|
Decimal |
Specifies the maximum wire length cap used by resizer to insert buffers during design repair. If set to 0, no buffers will be inserted. |
|
µm |
|
Decimal |
Specifies a margin for the slews during design repair. |
|
% |
|
Decimal |
Specifies a margin for the capacitances during design repair. |
|
% |
|
bool |
Invokes OpenROAD’s remove_buffers command to remove buffers from synthesis, which gives OpenROAD more flexibility when buffering nets. |
|
Repair Design (Post-Global Placement)¶
Runs a number of design “repairs” on a global-placed ODB file.
Importing
from openlane.steps.openroad import RepairDesignPostGPL
# or
from openlane.steps import Step
RepairDesignPostGPL = Step.factory.get("OpenROAD.RepairDesignPostGPL")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
|
Design Constraints (.sdc) |
|
Verilog Netlist (.nl.v) |
|
Powered Verilog Netlist (.pnl.v) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
str? |
The name of lowest layer to be used in routing the clock net. |
|
|
|
str? |
The name of highest layer to be used in routing the clock net. |
|
|
|
Decimal |
Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction. |
|
|
|
int |
Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches. |
|
|
|
List[Decimal] |
Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1. |
|
|
|
int? |
Diode cell padding; increases the width of diode cells during placement checks.. |
|
sites |
|
bool |
Allow congestion during global routing |
|
|
|
int |
The maximum number of iterations for global antenna repairs. |
|
|
|
int |
The maximum number of iterations waiting for the overflow to reach the desired value. |
|
|
|
int |
The margin to over fix antenna violations. |
|
% |
|
bool |
Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design. |
|
|
|
Decimal |
Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement. |
|
µm |
|
Decimal |
Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement. |
|
µm |
|
Decimal |
Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement. |
|
sites |
|
str |
A single regular expression designating nets or instances as “don’t touch” by design repairs or resizer optimizations. |
|
|
|
List[str]? |
A list of nets and instances as “don’t touch” by design repairs or resizer optimizations. |
|
|
|
List[str]? |
A list of fully-qualified IPVT corners to use during resizer optimizations. If unspecified, the value for |
|
|
|
bool |
Specifies whether or not to insert buffers on input ports when design repairs are run. |
|
|
|
bool |
Specifies whether or not to insert buffers on input ports when design repairs are run. |
|
|
|
bool |
Specifies whether or not to repair tie cells fanout when design repairs are run. |
|
|
|
bool |
Allows tie separation when performing design repairs. |
|
|
|
Decimal |
Specifies the maximum wire length cap used by resizer to insert buffers during design repair. If set to 0, no buffers will be inserted. |
|
µm |
|
Decimal |
Specifies a margin for the slews during design repair. |
|
% |
|
Decimal |
Specifies a margin for the capacitances during design repair. |
|
% |
|
bool |
Invokes OpenROAD’s remove_buffers command to remove buffers from synthesis, which gives OpenROAD more flexibility when buffering nets. |
|
Repair Design (Post-Global Routing)¶
Runs a number of design “repairs” on a global-routed ODB file.
Importing
from openlane.steps.openroad import RepairDesignPostGRT
# or
from openlane.steps import Step
RepairDesignPostGRT = Step.factory.get("OpenROAD.RepairDesignPostGRT")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
|
Design Constraints (.sdc) |
|
Verilog Netlist (.nl.v) |
|
Powered Verilog Netlist (.pnl.v) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
str? |
The name of lowest layer to be used in routing the clock net. |
|
|
|
str? |
The name of highest layer to be used in routing the clock net. |
|
|
|
Decimal |
Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction. |
|
|
|
int |
Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches. |
|
|
|
List[Decimal] |
Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1. |
|
|
|
int? |
Diode cell padding; increases the width of diode cells during placement checks.. |
|
sites |
|
bool |
Allow congestion during global routing |
|
|
|
int |
The maximum number of iterations for global antenna repairs. |
|
|
|
int |
The maximum number of iterations waiting for the overflow to reach the desired value. |
|
|
|
int |
The margin to over fix antenna violations. |
|
% |
|
bool |
Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design. |
|
|
|
Decimal |
Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement. |
|
µm |
|
Decimal |
Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement. |
|
µm |
|
Decimal |
Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement. |
|
sites |
|
str |
A single regular expression designating nets or instances as “don’t touch” by design repairs or resizer optimizations. |
|
|
|
List[str]? |
A list of nets and instances as “don’t touch” by design repairs or resizer optimizations. |
|
|
|
List[str]? |
A list of fully-qualified IPVT corners to use during resizer optimizations. If unspecified, the value for |
|
|
|
bool |
Enables running GRT before and after running resizer |
|
|
|
Decimal |
Specifies the maximum wire length cap used by resizer to insert buffers during post-grt design repair. If set to 0, no buffers will be inserted. |
|
µm |
|
Decimal |
Specifies a margin for the slews during post-grt design repair. |
|
% |
|
Decimal |
Specifies a margin for the capacitances during design post-grt repair. |
|
% |
Resizer Timing Optimizations (Post-Clock Tree Synthesis)¶
First attempt to meet timing requirements for a cell based on basic timing information after clock tree synthesis.
Standard cells may be resized, and buffer cells may be inserted to ensure that no hold violations exist and no setup violations exist at the current clock.
Importing
from openlane.steps.openroad import ResizerTimingPostCTS
# or
from openlane.steps import Step
ResizerTimingPostCTS = Step.factory.get("OpenROAD.ResizerTimingPostCTS")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
|
Design Constraints (.sdc) |
|
Verilog Netlist (.nl.v) |
|
Powered Verilog Netlist (.pnl.v) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
str? |
The name of lowest layer to be used in routing the clock net. |
|
|
|
str? |
The name of highest layer to be used in routing the clock net. |
|
|
|
Decimal |
Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction. |
|
|
|
int |
Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches. |
|
|
|
List[Decimal] |
Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1. |
|
|
|
int? |
Diode cell padding; increases the width of diode cells during placement checks.. |
|
sites |
|
bool |
Allow congestion during global routing |
|
|
|
int |
The maximum number of iterations for global antenna repairs. |
|
|
|
int |
The maximum number of iterations waiting for the overflow to reach the desired value. |
|
|
|
int |
The margin to over fix antenna violations. |
|
% |
|
bool |
Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design. |
|
|
|
Decimal |
Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement. |
|
µm |
|
Decimal |
Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement. |
|
µm |
|
Decimal |
Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement. |
|
sites |
|
str |
A single regular expression designating nets or instances as “don’t touch” by design repairs or resizer optimizations. |
|
|
|
List[str]? |
A list of nets and instances as “don’t touch” by design repairs or resizer optimizations. |
|
|
|
List[str]? |
A list of fully-qualified IPVT corners to use during resizer optimizations. If unspecified, the value for |
|
|
|
Decimal |
Specifies a time margin for the slack when fixing hold violations. Normally the resizer will stop when it reaches zero slack. This option allows you to overfix. |
|
ns |
|
Decimal |
Specifies a time margin for the slack when fixing setup violations. |
|
ns |
|
Decimal |
Specifies a max number of buffers to insert to fix hold violations. This number is calculated as a percentage of the number of instances in the design. |
|
|
|
Decimal |
Specifies a max number of buffers to insert to fix setup violations. This number is calculated as a percentage of the number of instances in the design. |
|
% |
|
bool |
Allows the creation of setup violations when fixing hold violations. Setup violations are less dangerous as they simply mean a chip may not run at its rated speed, however, chips with hold violations are essentially dead-on-arrival. |
|
|
|
bool |
Enables gate cloning when attempting to fix setup violations |
|
|
|
bool |
Experimental: attempt to fix hold violations before setup violations, which may lead to better timing results. |
|
Resizer Timing Optimizations (Post-Global Routing)¶
Second attempt to meet timing requirements for a cell based on timing information after estimating resistance and capacitance values based on global routing.
Standard cells may be resized, and buffer cells may be inserted to ensure that no hold violations exist and no setup violations exist at the current clock.
Importing
from openlane.steps.openroad import ResizerTimingPostGRT
# or
from openlane.steps import Step
ResizerTimingPostGRT = Step.factory.get("OpenROAD.ResizerTimingPostGRT")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
|
Design Constraints (.sdc) |
|
Verilog Netlist (.nl.v) |
|
Powered Verilog Netlist (.pnl.v) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
str? |
The name of lowest layer to be used in routing the clock net. |
|
|
|
str? |
The name of highest layer to be used in routing the clock net. |
|
|
|
Decimal |
Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction. |
|
|
|
int |
Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches. |
|
|
|
List[Decimal] |
Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1. |
|
|
|
int? |
Diode cell padding; increases the width of diode cells during placement checks.. |
|
sites |
|
bool |
Allow congestion during global routing |
|
|
|
int |
The maximum number of iterations for global antenna repairs. |
|
|
|
int |
The maximum number of iterations waiting for the overflow to reach the desired value. |
|
|
|
int |
The margin to over fix antenna violations. |
|
% |
|
bool |
Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design. |
|
|
|
Decimal |
Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement. |
|
µm |
|
Decimal |
Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement. |
|
µm |
|
Decimal |
Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement. |
|
sites |
|
str |
A single regular expression designating nets or instances as “don’t touch” by design repairs or resizer optimizations. |
|
|
|
List[str]? |
A list of nets and instances as “don’t touch” by design repairs or resizer optimizations. |
|
|
|
List[str]? |
A list of fully-qualified IPVT corners to use during resizer optimizations. If unspecified, the value for |
|
|
|
Decimal |
Specifies a time margin for the slack when fixing hold violations. Normally the resizer will stop when it reaches zero slack. This option allows you to overfix. |
|
ns |
|
Decimal |
Specifies a time margin for the slack when fixing setup violations. |
|
ns |
|
Decimal |
Specifies a max number of buffers to insert to fix hold violations. This number is calculated as a percentage of the number of instances in the design. |
|
% |
|
Decimal |
Specifies a max number of buffers to insert to fix setup violations. This number is calculated as a percentage of the number of instances in the design. |
|
% |
|
bool |
Allows setup violations when fixing hold. |
|
|
|
bool |
Enables gate cloning when attempting to fix setup violations |
|
|
|
bool |
Gates running global routing after resizer steps. May be useful to disable for designs where global routing takes non-trivial time. |
|
|
|
bool |
Experimental: attempt to fix hold violations before setup violations, which may lead to better timing results. |
|
Static Timing Analysis (Mid-PnR)¶
Performs Static Timing Analysis using OpenROAD on an OpenROAD database, mid-PnR, with estimated values for parasitics.
Importing
from openlane.steps.openroad import STAMidPNR
# or
from openlane.steps import Step
STAMidPNR = Step.factory.get("OpenROAD.STAMidPNR")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
Static Timing Analysis (Post-PnR)¶
Performs multi-corner Static Timing Analysis using OpenSTA on the post-PnR Verilog netlist, with extracted parasitics for both the top-level module and any associated macros.
During this step, the special variable OPENLANE_SDC_IDEAL_CLOCKS is exposed to SDC files with a value of 0. We encourage PNR SDC files to use propagated clocks at this stage based on this variable’s existence and value.
Importing
from openlane.steps.openroad import STAPostPNR
# or
from openlane.steps import Step
STAPostPNR = Step.factory.get("OpenROAD.STAPostPNR")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
Verilog Netlist (.nl.v) |
Standard Delay Format (.sdf) |
Standard Parasitics Extraction Format (.spef) |
Design Constraints (.sdc) |
OpenDB Database (.odb) |
LIB Timing Library Format (.lib) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
bool |
Prioritize the use of Netlists + SPEF files over LIB files if available for Macros. Useful if extraction was done using OpenROAD, where SPEF files are far more accurate. |
|
|
|
int? |
Maximum number of violators to list in violator_list.rpt |
|
|
|
List[(str| |
A variable that only exists for backwards compatibility with OpenLane <2.0.0 and should not be used by new designs. |
|
|
|
int? |
The maximum number of STA corners to run in parallel. If unset, this will be equal to your machine’s thread count. |
|
|
|
Path? |
Specifies the SDC file for STA during signoff |
|
Static Timing Analysis (Pre-PnR)¶
Performs hierarchical Static Timing Analysis using OpenSTA on the pre-PnR Verilog netlist, with all available timing information for standard cells and macros for multiple corners.
If timing information is not available for a Macro, the macro in question will be black-boxed.
During this step, the special variable OPENLANE_SDC_IDEAL_CLOCKS is exposed to SDC files with a value of 1. We encourage PNR SDC files to use ideal clocks at this stage based on this variable’s existence and value.
Importing
from openlane.steps.openroad import STAPrePNR
# or
from openlane.steps import Step
STAPrePNR = Step.factory.get("OpenROAD.STAPrePNR")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
Verilog Netlist (.nl.v) |
Standard Delay Format (.sdf) |
Design Constraints (.sdc) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
bool |
Prioritize the use of Netlists + SPEF files over LIB files if available for Macros. Useful if extraction was done using OpenROAD, where SPEF files are far more accurate. |
|
|
|
int? |
Maximum number of violators to list in violator_list.rpt |
|
|
|
List[(str| |
A variable that only exists for backwards compatibility with OpenLane <2.0.0 and should not be used by new designs. |
|
|
|
int? |
The maximum number of STA corners to run in parallel. If unset, this will be equal to your machine’s thread count. |
|
Tap/Decap Insertion¶
Places well TAP cells across a floorplan, as well as end-cap cells at the edges of the floorplan.
Importing
from openlane.steps.openroad import TapEndcapInsertion
# or
from openlane.steps import Step
TapEndcapInsertion = Step.factory.get("OpenROAD.TapEndcapInsertion")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
|
Design Constraints (.sdc) |
|
Verilog Netlist (.nl.v) |
|
Powered Verilog Netlist (.pnl.v) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
Decimal |
Specify the horizontal halo size around macros while cutting rows. |
|
µm |
|
Decimal |
Specify the vertical halo size around macros while cutting rows. |
|
µm |
OpenROAD Write Views¶
Write various layout views of an ODB design
Importing
from openlane.steps.openroad import WriteViews
# or
from openlane.steps import Step
WriteViews = Step.factory.get("OpenROAD.WriteViews")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
OpenDB Database (.odb) |
OpenDB Database (.odb) |
Design Exchange Format (.def) |
|
Design Constraints (.sdc) |
|
Verilog Netlist (.nl.v) |
|
Powered Verilog Netlist (.pnl.v) |
|
Powered Verilog Netlist For SDF Simulation (Without Fill Cells) (.pnl-sdf.v) |
|
Powered Verilog Netlist Without Physical Cells (Fill Cells and Diode Cells) (.pnl-npc.v) |
|
Library Exchange Format Generated by OpenROAD (.openroad.lef) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
bool |
Enables the connection of macros to the top level power grid. |
|
|
|
List[str]? |
Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names |
|
|
|
bool |
Enables the creation of global connections in PDN generation. |
|
|
|
Path? |
Specifies the SDC file used during all implementation (PnR) steps |
|
|
|
Path? |
Points to the DEF file to be used as a template. |
|
|
|
bool |
Generates cover obstructions (obstructions over the entire layer) for each layer where shapes are present |
|
Verilator¶
Verilator Lint¶
Lints inputs RTL Verilog files.
The linting is done with the defines for power and ground inputs on, as more macros are available with powered netlists than unpowered netlists.
Importing
from openlane.steps.verilator import Lint
# or
from openlane.steps import Step
Lint = Step.factory.get("Verilator.Lint")
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
List[Path] |
The paths of the design’s Verilog files. |
|
|
|
str? |
Specifies the name of the define used to guard power and ground connections in the input RTL. |
|
|
|
bool |
Include Verilog models of the PDK |
|
|
|
bool |
When a file references an include file, resolve the filename relative to the path of the referencing file, instead of relative to the current directory. |
|
|
|
bool |
When a latch is inferred by an |
|
|
|
List[str]? |
Preprocessor defines for input Verilog files |
|
|
|
List[str]? |
Linter-specific preprocessor definitions; overrides VERILOG_DEFINES for the lint step if exists |
|
Yosys¶
RTL/Netlist Equivalence Check¶
Importing
from openlane.steps.yosys import EQY
# or
from openlane.steps import Step
EQY = Step.factory.get("Yosys.EQY")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
Verilog Netlist (.nl.v) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
Path? |
A path to a file containing the latch mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the tri-state buffer mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the carry-select adder mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the ripple-carry adder mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the full adder mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the mux mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the mux4 mapping for Yosys. |
|
|
|
bool |
Activates Lighter, an experimental plugin that attempts to optimize clock-gated flip-flops. |
|
|
|
Path? |
An override to the custom DFF map file provided for the given SCL by Lighter. |
|
|
|
‘ALL’| |
Which log level for Yosys. At WARNING or higher, the initialization splash is also disabled. |
|
|
|
List[Path] |
The paths of the design’s Verilog files. |
|
|
|
List[str]? |
Preprocessor defines for input Verilog files. |
|
|
|
str? |
Specifies the name of the define used to guard power and ground connections in the input RTL. |
|
|
|
List[Path]? |
Specifies the Verilog |
|
|
|
List[str]? |
Key-value pairs to be |
|
|
|
bool |
Use the Synlig plugin to process files, which has better SystemVerilog parsing capabilities but may not be compatible with all Yosys commands and attributes. |
|
|
|
bool |
Uses -defer flag when reading files the Synlig plugin, which may improve performance by reading each file separately, but is experimental. |
|
|
|
Path? |
An optional override for the automatically generated EQY script for more complex designs. |
|
|
|
Path? |
This step will warn if this deprecated variable is used, as it indicates Macros are used without the new Macro object. |
|
|
|
bool |
Attempt to run EQY even if the PDK’s Verilog models are supported by this step. Will likely result in a failure. |
|
Generate JSON Header¶
Importing
from openlane.steps.pyosys import JsonHeader
# or
from openlane.steps import Step
JsonHeader = Step.factory.get("Yosys.JsonHeader")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
Design JSON Header File (.h.json) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
Path? |
A path to a file containing the latch mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the tri-state buffer mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the carry-select adder mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the ripple-carry adder mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the full adder mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the mux mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the mux4 mapping for Yosys. |
|
|
|
bool |
Activates Lighter, an experimental plugin that attempts to optimize clock-gated flip-flops. |
|
|
|
Path? |
An override to the custom DFF map file provided for the given SCL by Lighter. |
|
|
|
‘ALL’| |
Which log level for Yosys. At WARNING or higher, the initialization splash is also disabled. |
|
|
|
List[Path] |
The paths of the design’s Verilog files. |
|
|
|
List[str]? |
Preprocessor defines for input Verilog files. |
|
|
|
str? |
Specifies the name of the define used to guard power and ground connections in the input RTL. |
|
|
|
List[Path]? |
Specifies the Verilog |
|
|
|
List[str]? |
Key-value pairs to be |
|
|
|
bool |
Use the Synlig plugin to process files, which has better SystemVerilog parsing capabilities but may not be compatible with all Yosys commands and attributes. |
|
|
|
bool |
Uses -defer flag when reading files the Synlig plugin, which may improve performance by reading each file separately, but is experimental. |
|
Resynthesis¶
Like Synthesis
, but operates on the input netlist instead of RTL files.
Useful to process/elaborate on netlists generated by tools other than Yosys.
Some metrics will also be extracted and updated, namely:
design__instance__count
design__instance_unmapped__count
design__instance__area
Note that Yosys steps do not currently support gzipped standard cell dotlib files. They are however supported for macros:
https://github.com/YosysHQ/yosys/issues/4830
Importing
from openlane.steps.pyosys import Resynthesis
# or
from openlane.steps import Step
Resynthesis = Step.factory.get("Yosys.Resynthesis")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
Verilog Netlist (.nl.v) |
Verilog Netlist (.nl.v) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
Path? |
A path to a file containing the latch mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the tri-state buffer mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the carry-select adder mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the ripple-carry adder mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the full adder mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the mux mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the mux4 mapping for Yosys. |
|
|
|
bool |
Activates Lighter, an experimental plugin that attempts to optimize clock-gated flip-flops. |
|
|
|
Path? |
An override to the custom DFF map file provided for the given SCL by Lighter. |
|
|
|
‘ALL’| |
Which log level for Yosys. At WARNING or higher, the initialization splash is also disabled. |
|
|
|
bool |
Ignore multiple-driver warnings if they are connected to tri-state buffers on a best-effort basis. |
|
|
|
bool |
Generates names for netlist instances. This results in instance names that can be extremely long, but are more human-readable. |
|
|
|
‘AREA 0’| |
Strategies for abc logic synthesis and technology mapping. AREA strategies usually result in a more compact design, while DELAY strategies usually result in a design that runs at a higher frequency. Please note that there is no way to know which strategy is the best before trying them. |
|
|
|
bool |
Enables |
|
|
|
bool |
Replaces the ABC command |
|
|
|
bool |
Replaces the ABC command |
|
|
|
bool |
Passes D-flipflop cells through ABC for optimization (which can for example, eliminate identical flip-flops). |
|
|
|
bool |
Experimental: attempts a SAT-based remapping in all area and delay strategies before ‘retime’, which may improve PPA results. |
|
|
|
bool |
Experimental: uses the &nf delay-based mapper with a very high value instead of the amap area mapper, which may be better in some scenarios at recovering area. |
|
|
|
bool |
Enables inserting buffer cells for directly connected wires. |
|
|
|
bool |
Splits multi-bit nets into single-bit nets. Easier to trace but may not be supported by all tools. |
|
|
|
bool |
Enables |
|
|
|
‘flatten’| |
Affects how hierarchy is maintained throughout and after synthesis. ‘flatten’ flattens it during and after synthesis. ‘deferred_flatten’ flattens it after synthesis. ‘keep’ never flattens it. |
|
|
|
bool |
A flag that enables yosys to reduce the number of cells by determining shareable resources and merging them. |
|
|
|
‘YOSYS’| |
Adder type to which the \(add and \)sub operators are mapped to. Possible values are |
|
|
|
Path? |
Points to an extra techmap file for yosys that runs right after yosys |
|
|
|
bool |
“Elaborate” the design only without attempting any logic mapping. Useful when dealing with structural Verilog netlists. |
|
|
|
bool |
If |
|
|
|
bool |
Runs the booth pass as part of synthesis: See https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/booth.html |
|
|
|
‘high’| |
Whether to tie undefined values low or high. Explicitly provide null if you wish to simply leave them undriven. |
|
|
|
bool |
If true, Verilog-2001 attributes are omitted from output netlists. Some utilities do not support attributes. |
|
Synthesis¶
Performs synthesis and technology mapping on Verilog RTL files using Yosys and ABC, emitting a netlist.
Some metrics will also be extracted and updated, namely:
design__instance__count
design__instance_unmapped__count
design__instance__area
Note that Yosys steps do not currently support gzipped standard cell dotlib files. They are however supported for macros:
https://github.com/YosysHQ/yosys/issues/4830
Importing
from openlane.steps.pyosys import Synthesis
# or
from openlane.steps import Step
Synthesis = Step.factory.get("Yosys.Synthesis")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
Verilog Netlist (.nl.v) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
Path? |
A path to a file containing the latch mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the tri-state buffer mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the carry-select adder mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the ripple-carry adder mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the full adder mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the mux mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the mux4 mapping for Yosys. |
|
|
|
bool |
Activates Lighter, an experimental plugin that attempts to optimize clock-gated flip-flops. |
|
|
|
Path? |
An override to the custom DFF map file provided for the given SCL by Lighter. |
|
|
|
‘ALL’| |
Which log level for Yosys. At WARNING or higher, the initialization splash is also disabled. |
|
|
|
bool |
Ignore multiple-driver warnings if they are connected to tri-state buffers on a best-effort basis. |
|
|
|
bool |
Generates names for netlist instances. This results in instance names that can be extremely long, but are more human-readable. |
|
|
|
‘AREA 0’| |
Strategies for abc logic synthesis and technology mapping. AREA strategies usually result in a more compact design, while DELAY strategies usually result in a design that runs at a higher frequency. Please note that there is no way to know which strategy is the best before trying them. |
|
|
|
bool |
Enables |
|
|
|
bool |
Replaces the ABC command |
|
|
|
bool |
Replaces the ABC command |
|
|
|
bool |
Passes D-flipflop cells through ABC for optimization (which can for example, eliminate identical flip-flops). |
|
|
|
bool |
Experimental: attempts a SAT-based remapping in all area and delay strategies before ‘retime’, which may improve PPA results. |
|
|
|
bool |
Experimental: uses the &nf delay-based mapper with a very high value instead of the amap area mapper, which may be better in some scenarios at recovering area. |
|
|
|
bool |
Enables inserting buffer cells for directly connected wires. |
|
|
|
bool |
Splits multi-bit nets into single-bit nets. Easier to trace but may not be supported by all tools. |
|
|
|
bool |
Enables |
|
|
|
‘flatten’| |
Affects how hierarchy is maintained throughout and after synthesis. ‘flatten’ flattens it during and after synthesis. ‘deferred_flatten’ flattens it after synthesis. ‘keep’ never flattens it. |
|
|
|
bool |
A flag that enables yosys to reduce the number of cells by determining shareable resources and merging them. |
|
|
|
‘YOSYS’| |
Adder type to which the \(add and \)sub operators are mapped to. Possible values are |
|
|
|
Path? |
Points to an extra techmap file for yosys that runs right after yosys |
|
|
|
bool |
“Elaborate” the design only without attempting any logic mapping. Useful when dealing with structural Verilog netlists. |
|
|
|
bool |
If |
|
|
|
bool |
Runs the booth pass as part of synthesis: See https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/booth.html |
|
|
|
‘high’| |
Whether to tie undefined values low or high. Explicitly provide null if you wish to simply leave them undriven. |
|
|
|
bool |
If true, Verilog-2001 attributes are omitted from output netlists. Some utilities do not support attributes. |
|
|
|
List[Path] |
The paths of the design’s Verilog files. |
|
|
|
List[str]? |
Preprocessor defines for input Verilog files. |
|
|
|
str? |
Specifies the name of the define used to guard power and ground connections in the input RTL. |
|
|
|
List[Path]? |
Specifies the Verilog |
|
|
|
List[str]? |
Key-value pairs to be |
|
|
|
bool |
Use the Synlig plugin to process files, which has better SystemVerilog parsing capabilities but may not be compatible with all Yosys commands and attributes. |
|
|
|
bool |
Uses -defer flag when reading files the Synlig plugin, which may improve performance by reading each file separately, but is experimental. |
|
Synthesis (VHDL)¶
Performs synthesis and technology mapping on VHDL files using Yosys, GHDL and ABC, emitting a netlist.
Some metrics will also be extracted and updated, namely:
design__instance__count
design__instance_unmapped__count
design__instance__area
Note that Yosys steps do not currently support gzipped standard cell dotlib files. They are however supported for macros:
https://github.com/YosysHQ/yosys/issues/4830
Importing
from openlane.steps.pyosys import VHDLSynthesis
# or
from openlane.steps import Step
VHDLSynthesis = Step.factory.get("Yosys.VHDLSynthesis")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
Verilog Netlist (.nl.v) |
Configuration Variables¶
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
Path? |
A path to a file containing the latch mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the tri-state buffer mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the carry-select adder mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the ripple-carry adder mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the full adder mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the mux mapping for Yosys. |
|
|
|
Path? |
A path to a file containing the mux4 mapping for Yosys. |
|
|
|
bool |
Activates Lighter, an experimental plugin that attempts to optimize clock-gated flip-flops. |
|
|
|
Path? |
An override to the custom DFF map file provided for the given SCL by Lighter. |
|
|
|
‘ALL’| |
Which log level for Yosys. At WARNING or higher, the initialization splash is also disabled. |
|
|
|
bool |
Ignore multiple-driver warnings if they are connected to tri-state buffers on a best-effort basis. |
|
|
|
bool |
Generates names for netlist instances. This results in instance names that can be extremely long, but are more human-readable. |
|
|
|
‘AREA 0’| |
Strategies for abc logic synthesis and technology mapping. AREA strategies usually result in a more compact design, while DELAY strategies usually result in a design that runs at a higher frequency. Please note that there is no way to know which strategy is the best before trying them. |
|
|
|
bool |
Enables |
|
|
|
bool |
Replaces the ABC command |
|
|
|
bool |
Replaces the ABC command |
|
|
|
bool |
Passes D-flipflop cells through ABC for optimization (which can for example, eliminate identical flip-flops). |
|
|
|
bool |
Experimental: attempts a SAT-based remapping in all area and delay strategies before ‘retime’, which may improve PPA results. |
|
|
|
bool |
Experimental: uses the &nf delay-based mapper with a very high value instead of the amap area mapper, which may be better in some scenarios at recovering area. |
|
|
|
bool |
Enables inserting buffer cells for directly connected wires. |
|
|
|
bool |
Splits multi-bit nets into single-bit nets. Easier to trace but may not be supported by all tools. |
|
|
|
bool |
Enables |
|
|
|
‘flatten’| |
Affects how hierarchy is maintained throughout and after synthesis. ‘flatten’ flattens it during and after synthesis. ‘deferred_flatten’ flattens it after synthesis. ‘keep’ never flattens it. |
|
|
|
bool |
A flag that enables yosys to reduce the number of cells by determining shareable resources and merging them. |
|
|
|
‘YOSYS’| |
Adder type to which the \(add and \)sub operators are mapped to. Possible values are |
|
|
|
Path? |
Points to an extra techmap file for yosys that runs right after yosys |
|
|
|
bool |
“Elaborate” the design only without attempting any logic mapping. Useful when dealing with structural Verilog netlists. |
|
|
|
bool |
If |
|
|
|
bool |
Runs the booth pass as part of synthesis: See https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/booth.html |
|
|
|
‘high’| |
Whether to tie undefined values low or high. Explicitly provide null if you wish to simply leave them undriven. |
|
|
|
bool |
If true, Verilog-2001 attributes are omitted from output netlists. Some utilities do not support attributes. |
|
|
|
List[Path] |
The paths of the design’s VHDL files. |
|
Misc¶
Load Base Design Constraints File¶
Loads an SDC file specified as a configuration variable into the state object unaltered.
This Step exists for legacy compatibility and should not be used in new flows.
Importing
from openlane.steps.misc import LoadBaseSDC
# or
from openlane.steps import Step
LoadBaseSDC = Step.factory.get("Misc.LoadBaseSDC")
Inputs and Outputs¶
Inputs |
Outputs |
---|---|
Design Constraints (.sdc) |
Report Manufacturability (DRC, LVS, Antenna)¶
Importing
from openlane.steps.misc import ReportManufacturability
# or
from openlane.steps import Step
ReportManufacturability = Step.factory.get("Misc.ReportManufacturability")