Universal Flow Configuration Variables¶
These are flow configuration variables that are used commonly enough that we decided to expose them to all steps and all flows.
Configuration objects, be they JSON, Tcl or directly passed to the Python API, can freely override these values.
Note
?
indicates an optional variable, i.e., a value that may hold a value of
None
. OpenLane steps are expected to understand that these values are
optional and behave accordingly.
Variable Name |
Type |
Description |
Default |
Units |
---|---|---|---|---|
|
Path |
The directory of the design. Should be set via command-line arguments or :meth: |
|
|
|
Path |
The home path of all PDKs. Should be set via command-line arguments or :meth: |
|
|
|
str |
The name of the top level module of the design. Must be a valid C identifier, i.e., matches the regular expression |
|
|
|
str |
Specifies the process design kit (PDK). Must be a valid C identifier, i.e., matches the regular expression |
|
|
|
Decimal |
The clock period for the design. |
|
ns |
|
(str| |
The name(s) of the design’s clock port(s). |
|
|
|
(str| |
The name of the net input to root clock buffer. If unset, it is presumed to be equal to CLOCK_PORT. |
|
|
|
List[str]? |
Specifies the power nets/pins to be used when creating the power grid for the design. |
|
|
|
List[str]? |
Specifies the ground nets/pins to be used when creating the power grid for the design. |
|
|
|
Tuple[Decimal, Decimal, Decimal, Decimal]? |
Specific die area to be used in floorplanning. Specified as a 4-corner rectangle “x0 y0 x1 y1”. |
|
µm |
|
List[str]? |
Wildcards matching additional cells to exclude from both synthesis and PnR. |
|
|
|
Dict[str, Macro]? |
A dictionary of Macro definition objects. See |
|
|
|
List[Path]? |
Specifies miscellaneous LEF files to be loaded indiscriminately whenever LEFs are loaded. |
|
|
|
List[Path]? |
Specifies miscellaneous Verilog models to be loaded indiscriminately during synthesis. |
|
|
|
List[Path]? |
Specifies miscellaneous SPICE models to be loaded indiscriminately whenever SPICE models are loaded. |
|
|
|
List[Path]? |
Specifies LIB files of pre-hardened macros used in the current design, used during timing analyses (and during parasitics-based STA as a fallback). These are loaded indiscriminately for all timing corners. |
|
|
|
List[Path]? |
Specifies GDS files of pre-hardened macros used in the current design, used during tape-out. |
|
|
|
Path |
A fallback SDC file for when a step-specific SDC file is not defined. |
|