Universal Flow PDK Configuration Variables

These are variables that are to be defined by a process design kit’s configuration files for all steps and flows. For a PDK to be compatible with OpenLane, all non-Optional variables must be given a value.

Like with flow configuration variables, configuration objects can freely override these values.

Note

? indicates an optional variable, i.e., a value that does not need to be implemented by a PDK or an SCL. OpenLane steps are expected to understand that these values may hold a value of None in the input configuration and behave accordingly.

PDK-Level

These are variables that affect the entire PDK.

Variable Name	Type	Description	Units
STD_CELL_LIBRARY	str	Specifies the default standard cell library to be used under the specified PDK. Must be a valid C identifier, i.e., matches the regular expression [_a-zA-Z][_a-zA-Z0-9]+.
VDD_PIN	str	The power pin for the cells.
VDD_PIN_VOLTAGE	Decimal	The voltage of the VDD pin.
GND_PIN	str	The ground pin for the cells.
WIRE_LENGTH_THRESHOLD	Decimal?	A value above which wire lengths generate warnings.	µm
TECH_LEFS	Dict[str, Path]	Map of corner patterns to to technology LEF files. A corner not matched here will not be supported by OpenRCX in the default flow.
GPIO_PADS_LEF	List[Path]?	Path(s) to GPIO pad LEF file(s).
GPIO_PADS_LEF_CORE_SIDE	List[Path]?	Path(s) to GPIO pad LEF file(s) as used for routing (?).
GPIO_PADS_VERILOG	List[Path]?	Path(s) to GPIO pad Verilog models.
GPIO_PAD_CELLS	List[str]?	A list of pad cell name prefixes.
PRIMARY_GDSII_STREAMOUT_TOOL	str	Specify the primary GDSII streamout tool for this PDK. For most open-source PDKs, that would be ‘magic’.
DEFAULT_MAX_TRAN	Decimal?	Defines the default maximum transition value used in Synthesis and CTS. A minimum of 0.1 * CLOCK_PERIOD and this variable, if defined, is used.	ns
SIGNAL_WIRE_RC_LAYERS	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction. If unset, tools should use the average of layers between RT_MIN_LAYER and RT_MAX_LAYER. This variable will be moved to the relevant step(s) in the next version of OpenLane.
CLOCK_WIRE_RC_LAYERS	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction. If unset, tools should use the average of layers between RT_MIN_LAYER and RT_MAX_LAYER. This variable will be moved to the relevant step(s) in the next version of OpenLane.
DEFAULT_CORNER	str	The interconnect/process/voltage/temperature corner (IPVT) to use the characterized lib files compatible with by default.
STA_CORNERS	List[str]	A list of fully qualified IPVT (Interconnect, transistor Process, Voltage, and Temperature) timing corners on which to conduct multi-corner static timing analysis.
FP_TRACKS_INFO	Path	A path to the a classic OpenROAD .tracks file. Used by the floorplanner to generate tracks.
FP_TAPCELL_DIST	Decimal	The distance between tap cell columns.	µm
FP_IO_HLAYER	str	The metal layer on which to place horizontal IO pins, i.e., the top and bottom of the die.
FP_IO_VLAYER	str	The metal layer on which to place vertical IO pins, i.e., the top and bottom of the die.
RT_MIN_LAYER	str	The lowest metal layer to route on.
RT_MAX_LAYER	str	The highest metal layer to route on.

SCL-Level

These are variables that affect a specific standard-cell library.

Variable Name	Type	Description	Units
SCL_GROUND_PINS	List[str]	SCL-specific ground pins
SCL_POWER_PINS	List[str]	SCL-specific power pins
TRISTATE_CELLS	List[str]?	A list of cell names or wildcards of tri-state buffers.
FILL_CELL	List[str]	A list of cell names or wildcards of fill cells to be used in fill insertion.
DECAP_CELL	List[str]	A list of cell names or wildcards of decap cells to be used in fill insertion.
LIB	Dict[str, List[Path]]	A map from corner patterns to a list of associated liberty files. Exactly one entry must match the DEFAULT_CORNER.
CELL_LEFS	List[Path]	Path(s) to the cells’ LEF file(s).
CELL_GDS	List[Path]	Path(s) to the cells’ GDSII file(s).
CELL_VERILOG_MODELS	List[Path]?	Path(s) to cells’ Verilog model(s)
CELL_BB_VERILOG_MODELS	List[Path]?	Path(s) to cells’ black-box Verilog model(s)
CELL_SPICE_MODELS	List[Path]?	Path(s) to cells’ SPICE model(s)
SYNTH_EXCLUDED_CELL_FILE	Path	Path to a text file containing a list of (wildcards matching) cells to be excluded from the lib file in synthesis alone.
PNR_EXCLUDED_CELL_FILE	Path	Path to a text file containing a list of undesirable or bad (DRC-failed or complex pinout) cells or wildcards matching cells to be excluded from synthesis AND PnR.
OUTPUT_CAP_LOAD	Decimal	Defines the capacitive load on the output ports.	fF
MAX_FANOUT_CONSTRAINT	int	The max load that the output ports can drive to be used as a constraint on Synthesis and CTS.	cells
MAX_TRANSITION_CONSTRAINT	Decimal?	The max transition time (slew) from high to low or low to high on cell inputs in ns to be used as a constraint on Synthesis and CTS. If not provided, it is calculated at runtime as 10% of the provided clock period, unless that exceeds the PDK’s DEFAULT_MAX_TRAN value.	ns
MAX_CAPACITANCE_CONSTRAINT	Decimal?	The maximum capacitance constraint. If not provided, the constraint is not set in the SDC file which will fall back to the value set by the liberty file	pF
CLOCK_UNCERTAINTY_CONSTRAINT	Decimal	Specifies a value for the clock uncertainty/jitter for timing analysis.	ns
CLOCK_TRANSITION_CONSTRAINT	Decimal	Specifies a value for the clock transition/slew for timing analysis.	ns
TIME_DERATING_CONSTRAINT	Decimal	Specifies a derating factor to multiply the path delays with. It specifies the upper and lower ranges of timing.	%
IO_DELAY_CONSTRAINT	Decimal	Specifies the percentage of the clock period used in the input/output delays.	%
SYNTH_DRIVING_CELL	str	The cell to drive the input ports, used in synthesis and static timing analysis, in the format {cell}/{port}.
SYNTH_CLK_DRIVING_CELL	str?	The cell to drive the clock input ports, used in synthesis and static timing analysis, in the format {cell}/{port}. If not specified, SYNTH_DRIVING_CELL will be used.
SYNTH_TIEHI_CELL	str	Defines the tie high cell followed by the port that implements the tie high functionality, in the format {cell}/{port}.
SYNTH_TIELO_CELL	str	Defines the tie high cell followed by the port that implements the tie low functionality, in the format {cell}/{port}.
SYNTH_BUFFER_CELL	str	Defines a buffer port to be used by yosys during synthesis: in the format {cell}/{input_port}/{output_port}
WELLTAP_CELL	str	Defines the cell used for tap insertion.
ENDCAP_CELL	str	Defines so-called ‘end-cap’ cells- decap cells placed at either sides of a design.
PLACE_SITE	str	Defines the primary placement site in placement as specified in the technology LEF files, to generate the placement grid.
CELL_PAD_EXCLUDE	List[str]	Defines a list of cells to be excluded from cell padding.
DIODE_CELL	str?	Defines a diode cell used to fix antenna violations, in the format {name}/{port}.